Nexys3 Learning Notes 8: FT232 High Speed ​​UART

Continue with the previous section of the project, here to expand a UART peripheral on the XPS, with the onboard USB2UART chip FT232R to do a high-speed serial transmission test.

First open the previous ISE project, then double-click the mycpu module under the top-level module to open the hardware development platform XPS, as shown in Figure 1.

Legend has it that two UART peripheral IP cores are provided on the XPS bus, as shown in Figure 2, namely UART 16550-style and UART-Lite. This section will add a peripheral called UART-Lite, so the name is a streamlined small body UART peripherals, several contacts, and sure enough, the use of this Lite version for complex UART is really embarrassing, but For our experimental study, it is still more good, simple is easy to play, haha.

Figure 2 UART peripherals Double-click the AXI UART (Lite) option in Figure 2. The pop-up configuration page is shown in Figure 3. It is clear at a glance that the baud rate, data bits and parity bits can be set here. In addition, there are basically no options that can be set. Lite is here. In the hardware, the fixed UART transmission mode must be set once, and the software cannot be flexibly programmed. However, it is said that this UART-Lite is open source, and interested friends may wish to study it. It is also a very good job to transform this Lite very powerful.

Click on the small pdf icon in the upper right corner of Figure 3 to view the documentation for this peripheral, axi_uartlite_ds741.pdf. As shown in Figure 4, the UART-Lite functional block diagram shows that the peripherals contain the four most basic software-accessible registers, namely the Receive Data FIFO, the Transmit Data FIFO, and the status. Register (Status Register) and Control Register (Control Register).

After completing the UART-Lite configuration, click OK and the serial port shown in Figure 5 will pop up. With the default settings, the AXI bus interface of the UART-Lite peripheral automatically matches the on-chip AXI bus interface on the system's MicroBlaze processor.

Figure 5 Instantiating and Connecting IP Cores Adding new peripheral components requires re-clicking the XPS menu Hardware à Generate Netlist to generate a new netlist. After the new Netlist is successfully generated, return to ISE to view the corresponding View HDL InstanTIaTIon Template under mycpu.xmp. At this time, there are two signal interfaces axi_uartlite_0_RX_pin and axi_uartlite_0_TX_pin, which are the UART-Lite transceiver signals.

And re-edited embodiment of the top-level file, the top level code is modified as follows: module testled (clk, rst_n, led, uart_rx, uart_tx); input clk; // 100MHzinput rst_n; // low-level reset signal is output [7: 0] led; // connected to the LED input uart_rx; // UART data reception output uart_tx; // UART data transmission wire clk_100m; // clocking output 100MHzwire clk_50m; // clocking output 50MHzwire clk_25m; // clocking output 25MHzwire clk_12m5; / /clocking output 12.5MHzwire clk_locked; //clocking output completion flag ///--------------------------------- -----------------//IP Core Clocking Wizard instantiation ///---------- Begin Cut here for INSTANTIATION Template ---// INST_TAG myclocking uut_myclocking (// Clock in ports .CLK_IN1 (clk), // iN // Clock out ports .CLK_OUT1 (clk_100m), // OUT .CLK_OUT2 (clk_50m), // OUT .CLK_OUT3 (clk_25m), // OUT. CLK_OUT4(clk_12m5), // OUT // Status and control signals .RESET(!rst_n),// IN .LOCKED(clk_locked) ); // OUT// INST_TAG_END ------ End INSTANTIATION Template --------- //---------------------- -----------------------------// Instantiate the mysoc system (* BOX_TYPE = "user_black_box" *) mysoc uut_mysoc ( .RESET( Rst_n), .LEDS_TRI_O(led), .clock_generator_0_CLKIN_pin(clk_100m), .axi_uartlite_0_RX_pin(uart_rx), .axi_uartlite_0_TX_pin(uart_tx) ); endmodule pin assignment to the top two newly added signal interfaces, adding the following two statements to Testled.ucf can be: NET "uart_rx" LOC = N17; NET "uart_tx" LOC = N18; Finally recompile the entire ISE project and generate a .bit download file. Next, look at the software, open the SDK and locate Workspace to the SDK_workspace directory of the project. We clicked on the system.xml in the mysoc_hw_platform directory. At this point, we found that the new peripheral axi_uartlite_0 did not appear, indicating that the current software project does not update the current hardware project information in real time.

Obviously, in the current situation, we can't program and control the UART peripherals in the software. We must first update the hardware information of the system. Right click on the mysoc_hw_platform folder and select Change Hardware Platform Specification. As shown in Figure 8, relocate system.xml to the current project path (current project folder \mysoc\__xps\system.xml).

As shown in Figure 9, the newly added axi_uartlite_0 peripheral of the current instance appears in the rematched system.xml file.

Write software test code, realize the query mode (interrupt mode privilege students have not figured out, a little more confused, and then slowly study) serial data reception, and then send the data after negating. /* ------------------------------------------------ ------------ *//* Include File Definitions *//* --------------------------- --------------------------------- */ #include #include "xparameters.h" // The hardware configuration describing constants # include "xgpio_l.h" // This header file contains identifiers and driver functions # include "xil_io.h" // Contains the Xil_Out32 and Xil_In32 functions # include "xuartlite_l .h" // #define uchar unsigned char#define uint unsigned short /* --------------------------------- --------------------------- *//* main function *//* ------------- ----------------------------------------------- */ int main () {uchar rxdb; XUartLite_SetControlReg (XPAR_UARTLITE_0_BASEADDR, 0x10); // enable interrupt while (1) {if {rxdb = XUartLite_RecvByte (XPAR_UARTLITE_0_BASEADDR) (XUartLite_IsReceiveEmpty (XPAR_UARTLITE_0_BASEADDR)!); // XUartLite_ReadReg (XPAR_UARTLITE_0_BASEADDR, 0); XUartLite_SendByte ( XPAR_UARTLITE_0_BASEADDR,~rxdb); } } return 0;} Compile the project, then follow the previous section to burn the code into Nexys3. Note that two Mini-B cables are required to be interconnected with the PC, one for connecting the PC and J3, which is the download path mentioned in the previous section, and the other for connecting the PC and J13, that is, outside the UART-Lite. The path set. Or change the jumper cap of JP1 to 2-3PIN, connect J10 to a 5V DC power supply, and then continually sway the only Mini-B cable between J3 and J13, just like a privileged classmate ( However, this hot swapping does not know whether it will have a bad effect on the chip, although USB itself supports hot plugging). The FT232 chip is a USB to UART chip with one end for USB connection and the other end for UART communication. The so-called USB terminal, physical characteristics, is definitely a true USB, can be directly connected to the PC's USB port. From the perspective of the protocol, of course, it can indeed realize the data transmission of the USB protocol, but the simpler and more convenient method is to use the UART protocol to transmit data. At this time, it is a real "pseudo USB" - running the UART by USB . This seemingly magical chip is also a special thing. After connecting to the PC, if you don't want to install the driver (if you need to drive, you can download it from the official website of FTDI:), it will appear in the device manager by default. Under the port, as shown in Figure 10, "USB Serial Port (COM3)", remember this COM3, do not select the wrong port when sending and receiving data with the debug assistant.

Figure 10 Device Manager's new serial port

As shown in Figure 11, set the serial port debugging assistant port to COM3, baud rate 9600, data bit 8, no parity bit, for communication, send 55AA to return AA55.

Figure 11 Serial data transmission and reception

Since the FT232 chip uses USB to transmit the UART, it must be a bit too popular to have a reason. Of course, on the one hand, this chip will solve many new PCs without the RS232 serial port, and the old serial port's baud rate is usually no more than 115200bps, so the FT232 will come to challenge, so the privileged students also specially carried out high-speed transmission. The test, the highest nominal 921,600 bps, tossing the old half-day found that it does not work, this down, and finally the privileged classmates simply came to a software test that only did not receive, found that the original AA transmission data on the PC side has become CA or DA. One reasoning is that there may be an error in the peripheral baud rate, so the baud rate is lowered to 460800 bps, OK, and the error of the baud rate is further confirmed. Since the clock of the UART-Lite peripheral is divided by the CPU clock, and the CPU has a baud rate of 50 MHz, there is definitely an error in dividing the value of the non-integer multiple of 921600 bps. This simply solves the problem of raising the CPU clock to 100MHz. In fact, this solution does not solve the baud rate error problem in essence. If it is rigorous, I am afraid that it is more appropriate to adjust the frequency of an integer multiple of 961600bps as the peripheral clock. In short, the specific problem should be analyzed. It turns out that this high-speed UART is still reliable, and in the future it will not be able to get 115200bps on the UART. Reprinted from: privileged classmate's blog

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